/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef IRQ_NUM_E3650_LP_H
#define IRQ_NUM_E3650_LP_H

#define MB_MU_MESSAGE_READY_8_INTR_NUM                              (0U)
#define MB_MU_WAKEUP_8_INTR_NUM                                     (1U)
#define MB_SEMAPHORE_LOCK_FAIL_8_INTR_NUM                           (2U)
#define MB_SEMAPHORE_LOCK_STATUS_CHANGE_8_INTR_NUM                  (3U)
#define GPIO_SF1_SYNC_DGPIO_8_INTR_NUM                              (4U)
#define GPIO_SF1_ASYNC_DGPIO_8_INTR_NUM                             (4U)
#define GPIO_SF1_SYNC_GRP_48_INTR_NUM                               (5U)
#define GPIO_SF1_ASYNC_GRP_48_INTR_NUM                              (5U)
#define GPIO_SF1_SYNC_GRP_49_INTR_NUM                               (6U)
#define GPIO_SF1_ASYNC_GRP_49_INTR_NUM                              (6U)
#define GPIO_SF1_SYNC_GRP_50_INTR_NUM                               (7U)
#define GPIO_SF1_ASYNC_GRP_50_INTR_NUM                              (7U)
#define GPIO_SF1_SYNC_GRP_51_INTR_NUM                               (8U)
#define GPIO_SF1_ASYNC_GRP_51_INTR_NUM                              (8U)
#define GPIO_SF1_SYNC_GRP_52_INTR_NUM                               (9U)
#define GPIO_SF1_ASYNC_GRP_52_INTR_NUM                              (9U)
#define GPIO_SF1_SYNC_GRP_53_INTR_NUM                               (10U)
#define GPIO_SF1_ASYNC_GRP_53_INTR_NUM                              (10U)
#define GPIO_SF2_SYNC_DGPIO_8_INTR_NUM                              (11U)
#define GPIO_SF2_ASYNC_DGPIO_8_INTR_NUM                             (11U)
#define GPIO_SF2_SYNC_GRP_24_INTR_NUM                               (12U)
#define GPIO_SF2_ASYNC_GRP_24_INTR_NUM                              (12U)
#define GPIO_SF2_SYNC_GRP_25_INTR_NUM                               (13U)
#define GPIO_SF2_ASYNC_GRP_25_INTR_NUM                              (13U)
#define GPIO_SF2_SYNC_GRP_26_INTR_NUM                               (14U)
#define GPIO_SF2_ASYNC_GRP_26_INTR_NUM                              (14U)
#define GPIO_LP_SYNC_DGPIO_8_INTR_NUM                               (15U)
#define GPIO_LP_ASYNC_DGPIO_8_INTR_NUM                              (15U)
#define GPIO_LP_SYNC_GRP_32_INTR_NUM                                (16U)
#define GPIO_LP_ASYNC_GRP_32_INTR_NUM                               (16U)
#define GPIO_LP_SYNC_GRP_33_INTR_NUM                                (17U)
#define GPIO_LP_ASYNC_GRP_33_INTR_NUM                               (17U)
#define GPIO_LP_SYNC_GRP_34_INTR_NUM                                (18U)
#define GPIO_LP_ASYNC_GRP_34_INTR_NUM                               (18U)
#define GPIO_LP_SYNC_GRP_35_INTR_NUM                                (19U)
#define GPIO_LP_ASYNC_GRP_35_INTR_NUM                               (19U)
#define CR5_LP_NPMUIRQ0_INTR_NUM                                    (20U)
#define CR5_LP_CTI0_N_INTR_NUM                                      (21U)
#define SMC_SMC_WAKEUP_0_INTR_NUM                                   (22U)
#define WDT1_WDT_INTR_NUM                                           (23U)
#define WDT4_WDT_INTR_NUM                                           (24U)
#define WDT5_WDT_INTR_NUM                                           (25U)
#define WDT6_WDT_INTR_NUM                                           (26U)
#define WDT8_WDT_INTR_NUM                                           (27U)
#define WDT9_WDT_INTR_NUM                                           (28U)
#define EFUSEC_VIO_O0_INTR_NUM                                      (29U)
#define EFUSEC_VIO_O1_INTR_NUM                                      (29U)
#define R52_DBG_GASKET_DBG_INTR_NUM                                 (29U)
#define CR5_LP_DBG_GASKET_DBG_INTR_NUM                              (29U)
#define CR5_SE_DBG_GASKET_DBG_INTR_NUM                              (29U)
#define DMA1_PORT0_CH_0_1_2_3_INTR_NUM                              (30U)
#define DMA1_PORT0_CH_4_5_6_7_INTR_NUM                              (31U)
#define DMA1_PORT0_CH_8_9_10_11_INTR_NUM                            (32U)
#define DMA1_PORT0_CH_12_13_14_15_INTR_NUM                          (33U)
#define DMA1_PORT0_CH_16_17_18_19_INTR_NUM                          (34U)
#define DMA1_PORT0_CH_20_21_22_23_INTR_NUM                          (35U)
#define DMA1_PORT0_CH_24_25_26_27_INTR_NUM                          (36U)
#define DMA1_PORT0_CH_28_29_30_31_INTR_NUM                          (37U)
#define DMA1_PORT0_INTR_NUM                                         (38U)
#define DMA1_PORT1_CH_0_1_2_3_INTR_NUM                              (39U)
#define DMA1_PORT1_CH_4_5_6_7_INTR_NUM                              (40U)
#define DMA1_PORT1_CH_8_9_10_11_INTR_NUM                            (41U)
#define DMA1_PORT1_CH_12_13_14_15_INTR_NUM                          (42U)
#define DMA1_PORT1_CH_16_17_18_19_INTR_NUM                          (43U)
#define DMA1_PORT1_CH_20_21_22_23_INTR_NUM                          (44U)
#define DMA1_PORT1_CH_24_25_26_27_INTR_NUM                          (45U)
#define DMA1_PORT1_CH_28_29_30_31_INTR_NUM                          (46U)
#define DMA1_PORT1_INTR_NUM                                         (47U)
#define DMA2_PORT0_CH_0_1_2_3_INTR_NUM                              (48U)
#define DMA2_PORT0_CH_4_5_6_7_INTR_NUM                              (49U)
#define DMA2_PORT0_CH_8_9_10_11_INTR_NUM                            (50U)
#define DMA2_PORT0_CH_12_13_14_15_INTR_NUM                          (51U)
#define DMA2_PORT0_CH_16_17_18_19_INTR_NUM                          (52U)
#define DMA2_PORT0_CH_20_21_22_23_INTR_NUM                          (53U)
#define DMA2_PORT0_CH_24_25_26_27_INTR_NUM                          (54U)
#define DMA2_PORT0_CH_28_29_30_31_INTR_NUM                          (55U)
#define DMA2_PORT0_INTR_NUM                                         (56U)
#define DMA2_PORT1_CH_0_1_2_3_INTR_NUM                              (57U)
#define DMA2_PORT1_CH_4_5_6_7_INTR_NUM                              (58U)
#define DMA2_PORT1_CH_8_9_10_11_INTR_NUM                            (59U)
#define DMA2_PORT1_CH_12_13_14_15_INTR_NUM                          (60U)
#define DMA2_PORT1_CH_16_17_18_19_INTR_NUM                          (61U)
#define DMA2_PORT1_CH_20_21_22_23_INTR_NUM                          (62U)
#define DMA2_PORT1_CH_24_25_26_27_INTR_NUM                          (63U)
#define DMA2_PORT1_CH_28_29_30_31_INTR_NUM                          (64U)
#define DMA2_PORT1_INTR_NUM                                         (65U)
#define SEM1_O_SEM_CPU_INTR_NUM                                     (66U)
#define SEM2_O_SEM_CPU_INTR_NUM                                     (67U)
#define UART1_INTR_NUM                                              (68U)
#define UART2_INTR_NUM                                              (69U)
#define UART3_INTR_NUM                                              (70U)
#define UART4_INTR_NUM                                              (71U)
#define UART5_INTR_NUM                                              (72U)
#define UART6_INTR_NUM                                              (73U)
#define UART7_INTR_NUM                                              (74U)
#define UART8_INTR_NUM                                              (75U)
#define UART9_INTR_NUM                                              (76U)
#define UART10_INTR_NUM                                             (77U)
#define UART11_INTR_NUM                                             (78U)
#define UART12_INTR_NUM                                             (79U)
#define UART13_INTR_NUM                                             (80U)
#define UART14_INTR_NUM                                             (81U)
#define UART15_INTR_NUM                                             (82U)
#define UART16_INTR_NUM                                             (83U)
#define UART17_INTR_NUM                                             (84U)
#define UART18_INTR_NUM                                             (85U)
#define UART19_INTR_NUM                                             (86U)
#define UART20_INTR_NUM                                             (87U)
#define I2C1_INTR_NUM                                               (88U)
#define I2C2_INTR_NUM                                               (89U)
#define I2C3_INTR_NUM                                               (90U)
#define I2C4_INTR_NUM                                               (91U)
#define SPI1_INTR_NUM                                               (92U)
#define SPI2_INTR_NUM                                               (93U)
#define SPI3_INTR_NUM                                               (94U)
#define SPI4_INTR_NUM                                               (95U)
#define SPI5_INTR_NUM                                               (96U)
#define SPI6_INTR_NUM                                               (97U)
#define SPI7_INTR_NUM                                               (98U)
#define SPI8_INTR_NUM                                               (99U)
#define SPI9_INTR_NUM                                               (100U)
#define SPI10_INTR_NUM                                              (101U)
#define SPI11_INTR_NUM                                              (102U)
#define SPI12_INTR_NUM                                              (103U)
#define SPI13_INTR_NUM                                              (104U)
#define SPI14_INTR_NUM                                              (105U)
#define XSPI1_IRQ0_INTR_NUM                                         (106U)
#define XSPI1_IRQ1_INTR_NUM                                         (107U)
#define ENET1_SBD_INTR_NUM                                          (108U)
#define ENET1_SBD_PERCH_TX_O0_INTR_NUM                              (109U)
#define ENET1_SBD_PERCH_RX_O0_INTR_NUM                              (109U)
#define ENET1_SBD_PERCH_TX_O1_INTR_NUM                              (110U)
#define ENET1_SBD_PERCH_RX_O1_INTR_NUM                              (110U)
#define ENET1_SBD_PERCH_TX_O2_INTR_NUM                              (111U)
#define ENET1_SBD_PERCH_RX_O2_INTR_NUM                              (111U)
#define ENET1_LPI_INTR_NUM                                          (112U)
#define ENET1_PMT_INTR_NUM                                          (113U)
#define ENET2_SBD_INTR_NUM                                          (114U)
#define ENET2_SBD_PERCH_TX_O0_INTR_NUM                              (115U)
#define ENET2_SBD_PERCH_RX_O0_INTR_NUM                              (115U)
#define ENET2_SBD_PERCH_TX_O1_INTR_NUM                              (116U)
#define ENET2_SBD_PERCH_RX_O1_INTR_NUM                              (116U)
#define ENET2_SBD_PERCH_TX_O2_INTR_NUM                              (117U)
#define ENET2_SBD_PERCH_RX_O2_INTR_NUM                              (117U)
#define ENET2_LPI_INTR_NUM                                          (118U)
#define ENET2_PMT_INTR_NUM                                          (119U)
#define SENT1_CH_0_INTR_NUM                                         (120U)
#define SENT1_CH_1_INTR_NUM                                         (120U)
#define SENT1_CH_2_INTR_NUM                                         (120U)
#define SENT1_CH_3_INTR_NUM                                         (120U)
#define SENT1_CH_4_INTR_NUM                                         (120U)
#define SENT1_CH_5_INTR_NUM                                         (120U)
#define CANFD1_CANFD_INTR_NUM                                       (121U)
#define CANFD2_CANFD_INTR_NUM                                       (122U)
#define CANFD3_CANFD_INTR_NUM                                       (123U)
#define CANFD4_CANFD_INTR_NUM                                       (124U)
#define CANFD5_CANFD_INTR_NUM                                       (125U)
#define CANFD6_CANFD_INTR_NUM                                       (126U)
#define CANFD7_CANFD_INTR_NUM                                       (127U)
#define CANFD8_CANFD_INTR_NUM                                       (128U)
#define CANFD9_CANFD_INTR_NUM                                       (129U)
#define CANFD10_CANFD_INTR_NUM                                      (130U)
#define CANFD11_CANFD_INTR_NUM                                      (131U)
#define CANFD12_CANFD_INTR_NUM                                      (132U)
#define CANFD13_CANFD_INTR_NUM                                      (133U)
#define CANFD14_CANFD_INTR_NUM                                      (134U)
#define CANFD15_CANFD_INTR_NUM                                      (135U)
#define CANFD16_CANFD_INTR_NUM                                      (136U)
#define SEIP_PKE_INTR_NUM                                           (137U)
#define SEIP_SKE_INTR_NUM                                           (138U)
#define SEIP_HASH_INTR_NUM                                          (139U)
#define SEIP_TRNG_INTR_NUM                                          (140U)
#define SEIP_KEY_CHK_INTR_NUM                                       (141U)
#define SEIP_SOC_INTR_NUM                                           (141U)
#define SEIP_SENSOR_INTR_NUM                                        (142U)
#define SEIP_SEIP_ERR_INTR_NUM                                      (143U)
#define BTM1_O_BTM_INTR_NUM                                         (144U)
#define BTM2_O_BTM_INTR_NUM                                         (145U)
#define BTM3_O_BTM_INTR_NUM                                         (146U)
#define BTM4_O_BTM_INTR_NUM                                         (147U)
#define BTM5_O_BTM_INTR_NUM                                         (148U)
#define BTM6_O_BTM_INTR_NUM                                         (149U)
#define BTM7_O_BTM_INTR_NUM                                         (150U)
#define BTM8_O_BTM_INTR_NUM                                         (151U)
#define BTM9_O_BTM_INTR_NUM                                         (152U)
#define BTM10_O_BTM_INTR_NUM                                        (153U)
#define BTM11_O_BTM_INTR_NUM                                        (154U)
#define BTM12_O_BTM_INTR_NUM                                        (155U)
#define ETMR1_CHN_A_INTR_NUM                                        (156U)
#define ETMR1_CHN_B_INTR_NUM                                        (156U)
#define ETMR1_CHN_C_INTR_NUM                                        (156U)
#define ETMR1_CHN_D_INTR_NUM                                        (156U)
#define ETMR1_CNT_OVF_INTR_NUM                                      (157U)
#define ETMR2_CHN_A_INTR_NUM                                        (158U)
#define ETMR2_CHN_B_INTR_NUM                                        (158U)
#define ETMR2_CHN_C_INTR_NUM                                        (158U)
#define ETMR2_CHN_D_INTR_NUM                                        (158U)
#define ETMR2_CNT_OVF_INTR_NUM                                      (159U)
#define ETMR3_CHN_A_INTR_NUM                                        (160U)
#define ETMR3_CHN_B_INTR_NUM                                        (160U)
#define ETMR3_CHN_C_INTR_NUM                                        (160U)
#define ETMR3_CHN_D_INTR_NUM                                        (160U)
#define ETMR3_CNT_OVF_INTR_NUM                                      (161U)
#define ETMR4_CHN_A_INTR_NUM                                        (162U)
#define ETMR4_CHN_B_INTR_NUM                                        (162U)
#define ETMR4_CHN_C_INTR_NUM                                        (162U)
#define ETMR4_CHN_D_INTR_NUM                                        (162U)
#define ETMR4_CNT_OVF_INTR_NUM                                      (163U)
#define EPWM1_CHN_A_INTR_NUM                                        (164U)
#define EPWM1_CHN_B_INTR_NUM                                        (164U)
#define EPWM1_CHN_C_INTR_NUM                                        (164U)
#define EPWM1_CHN_D_INTR_NUM                                        (164U)
#define EPWM1_CNT_OVF_INTR_NUM                                      (165U)
#define EPWM2_CHN_A_INTR_NUM                                        (166U)
#define EPWM2_CHN_B_INTR_NUM                                        (166U)
#define EPWM2_CHN_C_INTR_NUM                                        (166U)
#define EPWM2_CHN_D_INTR_NUM                                        (166U)
#define EPWM2_CNT_OVF_INTR_NUM                                      (167U)
#define EPWM3_CHN_A_INTR_NUM                                        (168U)
#define EPWM3_CHN_B_INTR_NUM                                        (168U)
#define EPWM3_CHN_C_INTR_NUM                                        (168U)
#define EPWM3_CHN_D_INTR_NUM                                        (168U)
#define EPWM3_CNT_OVF_INTR_NUM                                      (169U)
#define EPWM4_CHN_A_INTR_NUM                                        (170U)
#define EPWM4_CHN_B_INTR_NUM                                        (170U)
#define EPWM4_CHN_C_INTR_NUM                                        (170U)
#define EPWM4_CHN_D_INTR_NUM                                        (170U)
#define EPWM4_CNT_OVF_INTR_NUM                                      (171U)
#define XTRG1_FUNC_INTR_NUM                                         (172U)
#define XTRG1_PWM_INTR_NUM                                          (173U)
#define XTRG1_CPT_INTR_NUM                                          (174U)
#define XTRG2_FUNC_INTR_NUM                                         (175U)
#define XTRG2_PWM_INTR_NUM                                          (176U)
#define XTRG2_CPT_INTR_NUM                                          (177U)
#define IOC_GPIO_SYNC_INTR_NUM                                      (178U)
#define IOC_GPIO_ASYNC_INTR_NUM                                     (178U)
#define RTC1_RTC_WAKEUP_INTR_NUM                                    (179U)
#define RTC1_RTC_PERIODICAL_INTR_NUM                                (180U)
#define RTC1_VIOLATION_INTR_NUM                                     (181U)
#define RTC2_RTC_WAKEUP_INTR_NUM                                    (182U)
#define RTC2_RTC_PERIODICAL_INTR_NUM                                (183U)
#define RTC2_VIOLATION_INTR_NUM                                     (184U)
#define IROMC_FUNC_INTR_NUM                                         (185U)
#define VD_SF_O_VDC_FUNC_INTR_NUM                                   (186U)
#define VD_LP_O_VDC_FUNC_INTR_NUM                                   (187U)
#define PT_SNS_SF_DIG_PVT_0_INTR_NUM                                (188U)
#define PT_SNS_SF_DIG_PVT_1_INTR_NUM                                (189U)
#define SCR_SAFB_SCR_APB_PSLVERR_INTR_NUM                           (190U)
#define SCR_LP_SCR_APB_PSLVERR_INTR_NUM                             (191U)
#define PMU_CORE_PMU_INTR_NUM                                       (192U)
#define RSTGEN_SF_RSTGEN_INTR_NUM                                   (193U)
#define U_CKGEN_SF_CKGEN_INTR_NUM                                   (194U)
#define RSTGEN_LP_RSTGEN_INTR_NUM                                   (195U)
#define U_CKGEN_LP_CKGEN_INTR_NUM                                   (196U)
#define SMC_SMC_INTR_NUM                                            (197U)
#define SADC1_O_SADC_INTR_NUM                                       (198U)
#define SADC2_O_SADC_INTR_NUM                                       (199U)
#define SADC3_O_SADC_INTR_NUM                                       (200U)
#define SADC4_O_SADC_INTR_NUM                                       (201U)
#define SADC5_O_SADC_INTR_NUM                                       (202U)
#define SADC6_O_SADC_INTR_NUM                                       (203U)
#define SADC7_O_SADC_INTR_NUM                                       (204U)
#define FS_32K_FS_32K_INTR_NUM                                      (205U)
#define ISTC_IRQ_INTR_NUM                                           (206U)
#define MAC_FUNC_INTR_NUM                                           (207U)
#define MPC_IRAMC1_FUNC_INTR_NUM                                    (207U)
#define MPC_IRAMC2_FUNC_INTR_NUM                                    (207U)
#define MPC_IRAMC3_FUNC_INTR_NUM                                    (207U)
#define MPC_XSPI1A_FUNC_INTR_NUM                                    (207U)
#define MPC_XSPI1B_FUNC_INTR_NUM                                    (207U)
#define MPC_MB_FUNC_INTR_NUM                                        (207U)
#define MPC_VIC2_FUNC_INTR_NUM                                      (207U)
#define MPC_CR5_SE_FUNC_INTR_NUM                                    (207U)
#define MPC_SEIP_FUNC_INTR_NUM                                      (207U)
#define MPC_R52_FUNC_INTR_NUM                                       (207U)
#define MPC_VIC1_FUNC_INTR_NUM                                      (207U)
#define MPC_CR5_LP_FUNC_INTR_NUM                                    (207U)
#define MPC_IRAMC_LP_FUNC_INTR_NUM                                  (207U)
#define MPC_MRAM1_FUNC_INTR_NUM                                     (207U)
#define MPC_MRAM2_FUNC_INTR_NUM                                     (207U)
#define MPC_MRAM3_FUNC_INTR_NUM                                     (207U)
#define MPC_MRAM4_FUNC_INTR_NUM                                     (207U)
#define MPC_MRAM5_FUNC_INTR_NUM                                     (207U)
#define PPC_APBMUX1_FUNC_INTR_NUM                                   (207U)
#define PPC_APBMUX2_FUNC_INTR_NUM                                   (207U)
#define PPC_APBMUX3_FUNC_INTR_NUM                                   (207U)
#define PPC_APBMUX4_FUNC_INTR_NUM                                   (207U)
#define PPC_APBMUX5_FUNC_INTR_NUM                                   (207U)
#define PPC_APBMUX6_FUNC_INTR_NUM                                   (207U)
#define PPC_APBMUX7_FUNC_INTR_NUM                                   (207U)
#define PPC_APBMUX8_FUNC_INTR_NUM                                   (207U)
#define CRAM1_FUNC_INTR_NUM                                         (207U)
#define CRAM2_FUNC_INTR_NUM                                         (207U)
#define CRAM3_FUNC_INTR_NUM                                         (207U)
#define CRAM4_FUNC_INTR_NUM                                         (207U)
#define GPIO_SF1_SGPIO_INTR_NUM                                     (208U)
#define GPIO_SF2_SGPIO_INTR_NUM                                     (209U)
#define GPIO_LP_SGPIO_INTR_NUM                                      (210U)
#define SEHC_SEHC_INTR_NUM                                          (211U)
#define SEHC_SEHC_WAKEUP_INTR_NUM                                   (212U)
#define DCDC_O_DCDC_FUNC_INTR_NUM                                   (213U)
#define LDO_LP_LP_LDO_FUNC_INTR_NUM                                 (214U)
#define WES_FUNC_INTR_NUM                                           (215U)
#define WES_WAKEUP_INTR_NUM                                         (216U)
#define DPE_DPE_INTR_NUM                                            (217U)
#define DPE_DPE_DVCAN_INTR_NUM                                      (218U)
#define DPE_DPE_CAN_INTR_NUM                                        (219U)
#define DPE_DPE_VCAN_0_INTR_NUM                                     (220U)
#define DPE_DPE_VCAN_1_INTR_NUM                                     (221U)
#define DPE_DPE_VCAN_2_INTR_NUM                                     (222U)
#define DPE_DPE_VCAN_3_INTR_NUM                                     (223U)
#define DPE_DPE_VCAN_4_INTR_NUM                                     (224U)
#define DPE_DPE_VCAN_5_INTR_NUM                                     (225U)
#define DPE_DPE_VCAN_6_INTR_NUM                                     (226U)
#define DPE_DPE_VCAN_7_INTR_NUM                                     (227U)
#define DPE_DPE_VCAN_8_INTR_NUM                                     (228U)
#define DPE_DPE_VCAN_9_INTR_NUM                                     (229U)
#define DPE_DPE_VCAN_10_INTR_NUM                                    (230U)
#define DPE_DPE_VCAN_11_INTR_NUM                                    (231U)
#define DPE_DPE_VCAN_12_INTR_NUM                                    (232U)
#define DPE_DPE_VCAN_13_INTR_NUM                                    (233U)
#define DPE_DPE_VCAN_14_INTR_NUM                                    (234U)
#define DPE_DPE_VCAN_15_INTR_NUM                                    (235U)
#define AWIC_SYNC_INTR_NUM                                          (236U)
#define AWIC_ASYNC_INTR_NUM                                         (237U)
#define IRAMC1_MBIST_INTR_NUM                                       (238U)
#define IRAMC2_MBIST_INTR_NUM                                       (239U)
#define IRAMC3_MBIST_INTR_NUM                                       (240U)
#define MRAM1_FUNC_INTR_NUM                                         (241U)
#define MRAM2_FUNC_INTR_NUM                                         (242U)
#define MRAM3_FUNC_INTR_NUM                                         (243U)
#define MRAM4_FUNC_INTR_NUM                                         (244U)
#define MRAM5_FUNC_INTR_NUM                                         (245U)
#define SACI1_I2S_INTR_NUM                                          (246U)
#define SACI1_PDM_INTR_NUM                                          (247U)
#define PFU_SE_FUNC_INTR_NUM                                        (248U)
#define AXB_R52A_AXB_DBG_INTR_NUM                                   (250U)
#define AXB_R52B_AXB_DBG_INTR_NUM                                   (251U)
#define AXB_LP_AXB_DBG_INTR_NUM                                     (252U)
#define AXB_SE_AXB_DBG_INTR_NUM                                     (253U)

#define IRQ_MAX_INTR_NUM                                            (254U)


#endif /* IRQ_NUM_E3650_LP_H */
